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1. general description the pca9629 is an i 2 c-bus controlled low-power cmos device that provides all the logic and control required to drive a four phase st epper motor. pca9629 is intended to be used with external high current drivers to drive the motor coils. the pca9629 supports three stepper motor drive formats: one-phase (wav e drive), two-phase, and half-step. in addition, when used as inputs, four general purpose input/outputs (gpios) allow sensing of logic level output from optical interrupter modules and generate active low interrupt signal on the int pin of pca9629. this is a useful feature in sensing home position of motor shaft or reference for step pulses. upon interrupt, the pca9629 can be programmed to automatically stop the motor or reverse the direction of rotation of motor. output wave train is programmable using co ntrol registers. the control registers are programmed via the i 2 c-bus. features built into the pca9629 provide highly flexible control of stepper motor, off-load bus master/micro and significantly reduce i 2 c-bus traffic. these include control of step size, number of steps per single command, number of full rotations and direction of rotation. a ramp-up on start and/or ramp-down on stop is also provided. the pca9629 is available in a 16-pin tssop package and is specified over the ? 40 ? c to +85 ? c industrial temperature range. 2. features and benefits ? generate motor coil drive phase sequence signals with four outputs for use with external high current drivers to off-load cpu ? four balanced push-pull type outputs capable of sinking 25 ma or sourcing 25 ma for glueless connection to external high cu rrent drivers needed to drive motor coils ? up to 1000 pf loads with 100 ns rise and fall times ? built-in oscillator requires no external components ? stepper motor drive control logic ? one-phase (wave drive), two-phase, and half-step drive format logic level outputs ? programmable step rate: 344.8 kpps to 0.3 pps with ? 5 % accuracy ? programmable ramp-up on start and ramp-down to stop ? programmable steps and rotation control ? sensor enabled drive control: linked to interrupt from i/o pins ? direction control of motor shaft ? selectable active hold, power off or released states for motor shaft pca9629 fm+ i 2 c-bus stepper motor controller rev. 1 ? 29 february 2012 product data sheet
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 2 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller ? four general purpose i/os: ? configured to sense logic level outputs from optical interrupter photo transistor circuit ? configured as outputs to drive (source/sink) leds or other loads up to 25 ma ? programmable interrupt mask control for input pins ? 4.5 v to 5.5 v operation ? 1 mhz fast-mode plus (fm+) i 2 c-bus serial interface with 30 ma high drive capability on sda output for driving high capacitive buses ? compliant with i 2 c-bus standard-mode (100 khz) and fast-mode (400 khz) speeds ? active low open-drain interrupt output ? active low reset (reset ) input pin resets device to power-up default state: can be used to recover from bus stuck condition ? programmable watchdog timer ? all call address allows programming of more than one device at the same time with the same parameters ? 16 programmable slave addresses using two address pins ? ? 40 ? c to +85 ? c operation ? esd protection exceeds 2000 v hbm per jesd22-a114 and 1000 v cdm per jesd22c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offered: tssop16 3. applications ? amusement machines ? gaming and slot machines ? consumer home appliances or toys ? industrial automation ? hvac and building climate control systems ? robotics 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version PCA9629PW tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2. ordering options type number topside mark temperature range PCA9629PW pca9629 t amb = ? 40 ? c to +85 ?c
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 3 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 5. block diagram remark: all i/os are set to inputs at power-up and reset. fig 1. pca9629 block diagram ad0 ad1 002aad902 i 2 c-bus control input filter pca9629 power-on reset scl sda v dd v ss control registers reset input register gpio and interrupt output control p0 int gpio interrupt handler loop delay timer ramp control steps, rotations and pulse width counters output phase sequence generator 200 k watchdog timer oscillator motor controller coil excitation logic p3 out0 out3
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 4 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for tssop16 PCA9629PW p0 v dd p1 sda p2 scl p3 int ad0 out0 ad1 out1 reset out2 v ss out3 002aad903 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 3. pin description symbol pin type description p0 1 i/o input/output 0 (output is 25 ma push-pull) p1 2 i/o input/output 1 (output is 25 ma push-pull) p2 3 i/o input/output 2 (output is 25 ma push-pull) p3 4 i/o input/output 3 (output is 25 ma push-pull) ad0 5 i address input 0 ad1 6 i address input 1 reset 7 i active low reset input with 1 ? s filter v ss 8 ground supply ground out3 9 o control 25 ma push-pull output 3 out2 10 o control 25 ma push-pull output 2 out1 11 o control 25 ma push-pull output 1 out0 12 o control 25 ma push-pull output 0 int 13 o active low interrupt output; open-drain scl 14 i serial clock line sda 15 i/o serial data line; open-drain capable of sinking 30 ma v dd 16 power supply supply voltage
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 5 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7. functional description refer to figure 1 ? pca9629 block diagram ? . 7.1 device address following a start conditio n, the bus master must send t he target slave address followed by a read or write operation. the slave address of the pca9629 is shown in figure 3 . slave address pins ad1 and ad0 choose one o f 16 slave addresses. to conserve power, no internal pull-up resistors are incorporated on ad1 and ad0. ta b l e 4 shows all 16 slave addresses by connecting the ad0 and ad1 to v dd , v ss , scl or sda. the last bit of the first byte defines the read ing from or writing to the pca9629. when set to logic 1 a read is selected, while logic 0 selects a write operation. fig 3. pca9629 device address table 4. pca9629 address map ad1 ad0 device family high-order address bits variable portion of address address a6 a5 a4 a3 a2 a1 a0 v ss v ss 010000040h v ss v dd 010000142h v dd v ss 010001044h v dd v dd 010001146h v ss scl010010048h v ss sda01001014ah v dd scl01001104ch v dd sda01001114eh scl v ss 010100050h sda v ss 010100152h scl v dd 010101054h sda v dd 010101156h sclscl010110058h sclsda01011015ah sdascl01011105ch sdasda01011115eh r/w 002aad905 0 1 0 a3 a2 a1 a0 programmable slave address fixed
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 6 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.2 command register following the successful acknowledgement of the slave address and a write bit, the bus master sends a byte to the pca9629. this byte is stored in the command register. at power-up, the command register defaults to 80h, with the ai bit set to ?1? and the lowest seven bits set to ?0?. the lowest six bits are used as a pointer to determine which register will be accessed. only a comman d register code with the six leas t significant bits equal to the 39 allowable values as defined in table 5 ? register summary ? are acknowledged. reserved or undefined command codes are not acknowledged. the most significant bit of the command register is for au to-increment. if the auto-increment flag is set, the six low-order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. the contents of these bits will roll over to ?00 0000? afte r the last register (address = 26h) is accessed. only the six least significant bits are affected by the ai flag. unused bits must be programmed with zeroes. 7.3 register definitions fig 4. command register 0 002aad906 1 0 0 0 0 0 0 d0 ai - d5 d4 d3 d2 d1 register number auto-increment default at power-up or after reset table 5. register summary register number d5 d4 d3 d2 d1 d0 name type function 00h 000000mode read/write mode register 01h 000001subadr1 read/write i 2 c-bus subaddress 1 02h 000010subadr2 read/write i 2 c-bus subaddress 2 03h 000011subadr3 read/write i 2 c-bus subaddress 3 04h 000100allcalladr read/write all call i 2 c-bus address 05h 000101wdtoi read/write watch dog time-out interval register 06h 000110wdcntl read/write watch dog control register 07h 000111ip read only input port register 08h 001000intstat read only interrupt status register 09h 001001op read/write output port register 0ah 001010ioc read/write i/o configuration register 0bh 001011msk read/write mask interrupt register 0ch 001100clrint write only clear interrupts 0dh 001101intmode read/write interrupt mode register 0eh 001110int_act_setupread/write interrupt action setup control register 0fh 001111int_mtr_setupread/write interrupt motor setup control register
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 7 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 10h 010000int_es_setup read/write interrupt extra steps setup control register 11h 010001int_auto_clr read/write interrupt auto clear control register 12h 010010setmode read/write output state on stop 13h 010011p hcntl read/write phase control register 14h 010100srotnl read/write steps per rotation low byte 15h 010101srotnh read/write steps per rotation high byte 16h 010110cwpwl read/write step pulse width for cw rotation low byte 17h 010111cwpwh read/write step pulse width for cw rotation high byte 18h 011000ccwpwl read/write step pulse width for ccw rotation low byte 19h 011001ccwpwh read/write step pulse width for ccw rotation high byte 1ah 011010cwscountl read/write number of steps cw low byte 1bh 011011cwscounth read/write number of steps cw high byte 1ch 011100ccwscountl read/write number of steps ccw low byte 1dh 011101ccwscounth read/write number of steps ccw high byte 1eh 011110cwrcountl read/write number of rotations cw low byte 1fh 011111cwrcounth read/write number of rotations cw high byte 20h 100000ccwrcountl read/write number of rotations ccw low byte 21h 100001ccwrcounth read/write number of rotations ccw high byte 22h 100010extrast eps0 read/write count value for ex tra steps or rotations for intp0 23h 100011extrast eps1 read/write count value for ex tra steps or rotations for intp1 24h 100100rmpcntl read/write ramp control register 25h 100101loopdly read/write loop delay time register 26h 100110mcntl read/write control start/stop motor 27h to ffh ------- - reserved table 5. register summary ?continued register number d5 d4 d3 d2 d1 d0 name type function
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 8 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.1 mode ? mode register 7.3.1.1 disable interrupt output pin (bit 5) this feature is useful when the hos t/micro/master does not want the int pin to toggle when interrupts occur. within pca9629, when interrupts are enabled and interrupt event occurs, the actions related to the interrupt event are still carr ied out. however, if bit 5 = 1, the int pin does not show the activation of interrupt because the pin is disabled. if bit 5 = 0, the micro sees the actual status of the int pin. the only exception to this rule is when the wa tchdog timer is enabled in the ?interrupt and reset? mode (see section 7.3.4.2 ). in this case, the inte rrupt line toggles when the watchdog timer times out (even though bit 5 of this register is a ?1?). th is is because in the ?interrupt and reset mode? the part gets rese t (and hence bit 5 is cleared) when the timer times out. 7.3.1.2 outputs change on stop (bit 4) this feature can be used to synchronize the starting of the motor across multiple pca9629 devices on the bus at approximately the same time (within few microseconds of one another). the host controller can progra m all the pca9629s on the bus and then issue the i 2 c-bus stop command. upon receiving the stop command, all the pca9629 devices on the bus start generating pulse sequences required to turn the motor. this feature is applicable only to the motor coil ou tputs of the device namely, out0 to out3. it is not applicable to the general purpose i/os (p0 to p3). table 6. mode - mode register (address 00h) bit description legend: * default value. address register bit access value description 00h mode 7 - 0* not used 6 - 0* not used 5 r/w 1 disable int output pin 0* enable int output pin 4 r/w 1 outputs change on i 2 c-bus ack 0* outputs change on i 2 c-bus stop command 3 r/w 1 pca9629 responds to i 2 c-bus subaddress 1 0* pca9629 does not respond to i 2 c-bus subaddress 1 2 r/w 1 pca9629 responds to i 2 c-bus subaddress 2 0* pca9629 does not respond to i 2 c-bus subaddress 2 1 r/w 1 pca9629 responds to i 2 c-bus subaddress 3 0* pca9629 does not respond to i 2 c-bus subaddress 3 0 r/w 1* pca9629 responds to all call i 2 c-bus address 0 pca9629 does not respond to all call i 2 c-bus address
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 9 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.2 subadr1 to subadr3 ? i 2 c-bus subaddress 1 to 3 subaddresses are programmable through the i 2 c-bus. default power-up values are e2h, e4h, e8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding bits [3:1] in mode register is equal to 0). once subaddresses have been programmed to their right values, bits [3:1] (mode register) must be set to logic 1 in order to have the device acknowledging these addresses. only the seven msbs representing the i 2 c-bus subaddress are valid. the lsb in subadrx register is a read-only bit (0). when subaddress control bits [3:1] in mode register is set to logic 1, the corresponding i 2 c-bus subaddress can be used during either an i 2 c-bus read or write sequence. 7.3.3 allcalladr ? all call i 2 c-bus address the all call i 2 c-bus address allows all the pca9629s on the bus to be programmed at the same time (bit 0 in register mode must be equal to 1 (power-up default state)). this address is programmable through the i 2 c-bus and can be used during either an i 2 c-bus read or write sequence. only the seven msbs representing the all call i 2 c-bus address are valid. the lsb in allcalladr register is a read-only bit (0). if bit 0 in mode register = 0, the device does not acknowledge the address programmed in register allcalladr. table 7. subadr1 to subadr3 - i 2 c-bus subaddress registers 1 to 3 (addresses 01h, 02h 03h) bit description legend: * default value. address register bit symbol access value description 01h subadr1 7:1 a1[7:1] r/w 1110 001* i 2 c-bus subaddress 1 0 a1[0] r only 0* reserved 02h subadr2 7:1 a2[7:1] r/w 1110 010* i 2 c-bus subaddress 2 0 a2[0] r only 0* reserved 03h subadr3 7:1 a3[7:1] r/w 1110 100* i 2 c-bus subaddress 3 0 a3[0] r only 0* reserved table 8. allcalladr - all call i 2 c-bus address register (address 04h) bit description legend: * default value. address register bit symbol access value description 04h allcalladr 7:1 ac[7:1] r/w 1110 000* allcall i 2 c-bus address register 0 ac[0] r only 0* reserved
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 10 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.4 watchdog timer the purpose of the watchdog timer is to reco ver the pca9629 if the system it is used in enters an erroneous state. when the timer times out, the watchdog generates an interrupt to the host controller and, if programmed for reset, resets pca9629 if the user program fails to ?feed? the watchdog. to feed t he watchdog, the user simply addresses the pca9629 ([start + slave address + start] or [start + slave address + stop]) within the watchdog time-out inte rval. only this sequence resets the watchdog. watchdog timer features: ? can be programmed to reset the pca9629 to por state if it is not periodically addressed ? enabled by software, but requires a hardware reset or a watchdog reset to be disabled ? flag to indicate watchdog reset ? programmable 8-bit timer with internal prescaler ? selectable time period from one second to 255 seconds the watchdog timer should be used in the following manner: ? set the time-out interval value in wdtoi register ? set the mode of operation (interrupt only or interrupt and reset) and enable the watchdog using the wdcntl register ? watchdog should be fed by periodically addressing pca9629 before the watchdog timer underflows to prevent reset/interrupt ? watchdog control register, wdcnt l, can be read at any time to determi ne the status of the watchdog operation 7.3.4.1 wdtoi ? watchdog time-out interval register the watchdog time-out interval should be programmed in this register. the default value is ffh, which indicates a 255 second time-out in terval. the smallest va lue for the time-out interval is 01h, which indicates a one-se cond time-out interval. watchdog operation cannot be enabled with a zero second time-out interval. if user writes a zero value to this register, the timer does not start. table 9. wdtoi - watchdog time-out interval register (address 05h) bit description legend: * default value. address register bit access value description 05h wdtoi 7:0 r/w ffh* watchdog time-out interval
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 11 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.4.2 wdcntl ? watchdog control register [1] use bit 4 to clear this bit. [2] reading wdcntl register clears this bit. this register controls the operation of the watchdog timer. watchdog timer can be enabled by setting the wden bit of this register. wden is a set-only bit. once set (enabled), this bit cannot be cleared by software. it can be cleared only with a hardware reset or watchdog reset. the wdmod bit determines the mode of operati on. this bit is a set-only bit. there are two modes of operation: ? interrupt only mode : this is the default mode of op eration. in this mode, when the watchdog timer times out, the interrupt fl ag is set (wdint) and an interrupt is generated to the host controller. ? interrupt and re set mode: in this mode, when the wa tchdog timer times out, the reset flag is set (wdrst) and an interrupt is generated to host controller and resets the chip to por state. wdint flag: this flag can be cleared by wr iting a ?1? to bit 4 of this register. wdrst flag: this flag indicates that a watchd og reset has occurred. this flag does not get cleared by the watchdog reset. after a wa tchdog reset event, the host controller can read this bit to determine if a reset had occurred. the wdrst flag gets cleared after it is read or after an external reset is applied. before enabling the watchdog timer, the watchd og flags (interrupt flag and reset flag) must be cleared (if they are set). the interrupt flag is cleared by using bit 4 of the wdcntl register and the reset flag is clea red just by reading the wcntl register. table 10. wdmod - watchdog control register (address 06h) bit description legend: * default value. address register bit access value description 06h wdcntl 7:5 read only 000* reserved. 4 write only 1 clear wdint flag. 0* read value. 3 read only 1 wdint: watchdog interrupt flag set. [1] 0* wdint: watchdog interrupt flag not set. 2 read only 1 wdrst: watchdog reset flag. [2] 0* wdrst: watchdog reset flag not set. 1 r/w 1 wdmod: watchdog interrupt and reset mode (set only). 0* wdmod: watchdog interrupt only mode. 0 r/w 1 wden: watchdog enabled (set only). 0* wden: watchdog disabled.
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 12 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.5 gpios and interrupts 7.3.5.1 ip ? input port register this register is read-only. they reflect the in coming logic levels of the port pins p0 to p3, regardless of whether the pin is defined as an input or an output by the i/o configuration register. writes to this register have no effect. 7.3.5.2 intstat ? interrupt status register this register reflects the status of an interrupt. intstat is a read-only register. intp0 to intp3 interrupt caused by in put port pins p0 to p3, respectively. upon power-up or activation of hardware reset by reset pin, intstat register bits [3:0] are cleared (= 0), thus clearing the interrupt flags. change in logic level at gpio pins p0 to p3 configured as inputs will cause gener ation of interrupt w hen not masked using msk register. the corresponding flag bit in this register is set and latched until cleared. 7.3.5.3 op ? output port register this register is an output-only port. it reflects the outgoing logic levels of the pins defined as outputs by ioc register. bit values in this register have no effect on pins defined as inputs. in turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. only the lower four bits are used and p0 to p3 are affected by this register. table 11. ip - input port register (address 07h) bit description legend: * default value ?x? is determined by the externally applied logic level. address register bit access value description 07h ip 7:4 read only 0h* reserved 3:0 read only xh* reflects incoming logic levels of i/o p0 to p3 table 12. intstat - interrupt status register (address 08h) bit description legend: * default value. address register bit access value description 08h intstat 7:4 - 0* reserved 3:0 read only 1 intp3 flag set 0* intp3 flag clear 1 intp2 flag set 0* intp2 flag clear 1 intp1 flag set 0* intp1 flag clear 1 intp0 flag set 0* intp0 flag clear table 13. op - output port register (address 09h) bit description legend: * default value. address register bit access value description 09h op 7:4 - 0000* reserved 3:0 r/w 0000* reflects outgoing logic levels of i/o p0 to p3
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 13 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.5.4 ioc ? i/o configuration register the lower four bits of this register configures the direction of the i/o pins p0 to p3. if a bit in [3:0] is set (written with logic 1), the corresponding port pin is enabled as an input with high-impedance output driver. if the bit is cl eared (written with logic 0), the corresponding port pin is enabled as an output. at reset, the device?s ports p0 to p3 are inputs. 7.3.5.5 msk ? mask interrupt register upon power-up, all the internal interrupt latches are reset and interrupt flags cleared and interrupt mask bits [3:0] are set to logic 1, thus disabling interrupts from input ports p0 to p3. interrupts may be enabled by setting corresponding mask bits to logic 0. an additional control to enable or disable the int pin is provided by mode control register bit 5 (mode[5]). refer to ta b l e 6 . table 14. ioc - i/o configuration regi ster (address 0ah) bit description legend: * default value. address register bit access value description 0ah ioc 7:4 - 0* reserved 3 r/w 1* p3 will be configured as input 0 p3 will be configured as output 2 r/w 1* p2 will be configured as input 0 p2 will be configured as output 1 r/w 1* p1 will be configured as input 0 p1 will be configured as output 0 r/w 1* p0 will be configured as input 0 p0 will be configured as output fig 5. simplified schematic for gpio control 002aaf869 ioc - i/o configuration register op - output port register ip - input port register p0 to p3 read/write access from i 2 c-bus read only access from i 2 c-bus table 15. msk - interrupt mask regist er (address 0bh) bit description legend: * default value. address register bit access value description 0bh msk 7:4 - 0* reserved 3 r/w 1* disables interrupt for i/o p3 0 enables interrupt for i/o p3 2 r/w 1* disables interrupt for i/o p2 0 enables interrupt for i/o p2 1 r/w 1* disables interrupt for i/o p1 0 enables interrupt for i/o p1 0 r/w 1* disables interrupt for i/o p0 0 enables interrupt for i/o p0
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 14 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.5.6 clrint ? clear interrupts register interrupt flags can be cleared by bits [3:0] when set to logic 1. 7.3.5.7 intmode ? interrupt mode register when interrupt( s) are enabled, bits [3:0] determine whether rising edge or falling edge of signal at p0 to p3 causes the interrupt to be generated. interrupts are latched and flag(s) are set in the corresponding bits of intstat register. when interrupts are masked using msk register, these bits have no effect. table 16. clrint - clear interrupts regi ster (address 0ch) bit description legend: * default value. address register bit access value description 0ch clrint 7:4 - 0* reserved 3 write only 1 clear intp3 flag 0* read value 2 write only 1 clear intp2 flag 0* read value 1 write only 1 clear intp1 flag 0* read value 0 write only 1 clear intp0 flag 0* read value table 17. intmode - interrupt mode register (address 0dh) bit description legend: * default value. address register bit access value description 0dh intmode 7:4 - 0* reserved 3 r/w 1 interrupt occurs on falling edge for p3 0* interrupt occurs on rising edge for p3 2 r/w 1 interrupt occurs on falling edge for p2 0* interrupt occurs on rising edge for p2 1 r/w 1 interrupt occurs on falling edge for p1 0* interrupt occurs on rising edge for p1 0 r/w 1 interrupt occurs on falling edge for p0 0* interrupt occurs on rising edge for p0
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 15 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.6 interrupt based motor control interrupt mechanisms from gpios 0 and 1 (intp0 and intp1) can be used to control the motor operation. interrupts from gpios 2 and 3 are not used for motor control. they behave as normal gpio interrupts. in the follo wing sections, the word interrupt refers only to intp0 and intp1. the following actions c an be performed upon the occurrence of an interrupt: ? stop the motor ? reverse the direction of motion ? move extra steps/rotations and then, st op the motor or reverse its direction. only interrupts that occurred after the motor was started are acted upon. when an interrupt occurs, it is latched and t he programmed action is performed. the microcontroller has to clear the interrupt before another occurrence of the same interrupt otherwise the second occurren ce will not be acted upon. th e following four registers, int_act_setup, int_mtr_set up, int_es_setup and int_auto_clr are used to program the various interrupt based control feat ures of the motor. to enable the interrupt based control of the motor, bit 0 of the int_act_setup register must be set. fig 6. pca9629 interrupt logic 002aaf870 mode[5] int wdint wdrst watchdog timer dq 1 clrint[3] dq 1 clrint[0] intmode rising edge detector falling edge detector p0 ioc[0] msk[0] intmode rising edge detector falling edge detector p3 ioc[3] msk[3]
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 16 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.6.1 int_act_setup ? interrupt action setup control register if the interrupt based control is disabled, then values programmed in the following three registers (int_mtr_setup, int_es_setup and int_auto_clr) have no effect on the motor operation. bit 4 of this register determines whethe r the values programmed in extrasteps0 and extrasteps1 registers represent the number of steps or number of rotations (see section 7.3.16 ). 7.3.6.2 int_mtr_setup ? interrupt motor setup control register when an interrupt occurs, if the motor is programmed to stop on that inte rrupt, the following sequence of events takes place in the given order: 1. if extra steps feature is enabled for that interrupt (see int_es_setup, section 7.3.6.3 ) then extra steps (/rotations) will occur. 2. if ramp down is enabled (see rmpcntl, section 7.3.17 ), the motor starts ramping down. 3. motor stops. when an interrupt occurs, if the motor is programmed to reverse direction on that interrupt, the following sequence of events takes place: 1. if extra steps feature is enabled for that interrupt (see int_es_setup, section 7.3.6.3 ) then extra steps (/rotations) occurs in the current direction of motion. 2. the motor stops for the amount of time specified in the loopdly timer register. 3. motor reverses its direction of rotation. table 18. int_act_setup - interrupt action setup control register (address 0eh) bit description legend: * default value. address register bit access value description 0eh int_act_setup 7:5 - - not used 4 r/w 1 unit for extrasteps for both p0 and p1 counter is number of full rotations 0* unit for extrasteps for both p0 and p1 counter is number of steps 3:1 - - not used 0 r/w 1 enable interrupt based control of motor 0* disable interrupt based control of motor table 19. int_mtr_setup - in terrupt motor setup contro l register (address 0fh) bit description legend: * default value. address register bit access value description 0fh int_mtr_setup 7:2 r - reserved 1:0 r/w 11 reverse motor on int caused by p0 or p1 10 stop motor on int caused by p0 or p1 01 stop motor on int caused by p1 00* stop motor on int caused by p0
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 17 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.6.3 int_es_setup ? interrupt ex tra steps setup control register this register can be used to enable / disable the extra steps feature for each interrupt. extra steps feature is used to make the motor rotate a specified amount of steps/rotations from the point of an interrupt oc currence. 7.3.6.4 int_auto_clr ? inte rrupt auto clear register this register provides a mechanism to clear the two interrupts (intp0 and intp1) automatically without the occurrence of one interrupt clears the other without the microcontroller. the auto clear feature is disabled by default. this feature is only available fo r interrupts that directly affect the operation of the motor as defined by the int_mtr_setup register (see section 7.3.6.2 ). for example, if intp0 is used to stop the motor then it can be auto matically cleared by its pair intp1. however intp1 should be manually cleared (through i 2 c-bus write to the clrint register). if both the interrupts are used to control the motor operation (int_mtr_setup = 10 or 11), then all options of this register are valid. any inte rrupt that is not automatically cleared by its pair should be manually cleared through i 2 c-bus write. the auto clear mechanism can be used to create various motor movement patterns without being supervised by the microcontroller. for example, consider an application where the direction of motor rotation must be automatically reversed based on signals from two sensors placed apart from each other (sometimes referred to as ?home? positions) in a continuous manner without involving the microcontroller. the following example shows how to program the device for such an operation. table 20. int_es_setup - interrupt extra steps setup control register (address 10h) bit description legend: * default value. address register bit access value description 10h int_es_setup 7:2 r 0000 00 reserved 1:0 r/w 11 enable extrasteps on both intp0 and intp1 10 enable extrasteps only on intp1 01 enable extrasteps only on intp0 00* disable extrasteps for both intp0 and intp1 table 21. int_auto_clr - interrupt auto clear register (address 11h) bit description legend: * default value. address register bit access value description 11h int_auto_clr 7:2 - 0* reserved 1:0 r/w 11 intp0 auto clears intp1 10 intp1 auto clears intp0 01 intp0 auto clears intp1; intp1 auto clears intp0 00* int auto clear for intp0, intp1 disabled
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 18 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller example: this example assumes that two position sensors are located spaced apart and a drive mechanism is needed to move an object back and forth between these two sensors. figure 7 shows this application use case. driving the stepper motor causes movement of the object toward one of the s ensors. logic level output of one sensor is connected to input pin p0 and the other to p1. p0 and p1 are configured as inputs . at power-up, intp0 to intp3 flag s intstat[3:0] are clear (= 0). set int_act_setup[0] = 1, enable interrupt based motor control. set int_mtr_setup[1:0] = 11, reverse motor on interrupt caused by p0 or p1. set int_auto_clr[1:0] = 01, intp0 clears intp1; intp1 clears intp0. start motor by writing mcntl register and after some time, position sensor causes input logic at p0 to toggle. when the input logic level at p0 changes, the interrupt caused by p0 is latched; intp0 flag in intstat is set (= 1). since int_act_setup[0] = 1 and int_mtr_ setup[1:0] = 11 (reverse motor on interrupt caused by p0 or p1), the motor direction is reversed and the intp1 flag is cleared (since intp0 clears intp1). this allo ws interrupt generation at the end of reverse movement by sensor at p1. fig 7. example of controlling doll head movement between two home positions 002aae760 pca9629 v dd scl sda int reset ad1 ad0 master controller v ss p0 p1 p2 p3 12 v external high current driver generates intp1 sensor 1 electrical stepper motor position b sensor 0 generates intp0 position a out0 out1 out2 out3 5 v 2 k 1.1 k 1.6 k 1.6 k 3.3 v int rst m
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 19 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.7 setmode ? output state on stop control register this register determines th e condition of motor output pins when stopped, one of logic 0 or hold (last state). 7.3.8 phcntl ? phase control register this register is used to configure the phas e of the output waveforms at the output ports out0 to out3 to drive the mo tor coils (with external high current drivers). one of the following three modes of drive method can be selected using these bits: ? one-phase drive (wave drive) ? two-phase drive ? half-step drive the phase drive can be changed at any ti me by writing to phcntl[1:0] bits. 7.3.9 srotnl, srotnh ? steps per rotation registers this register determines how many steps are needed to execute one full turn of motor shaft (360 ? ). this register should have a non-zero value if the requested operation is rotations (see section 7.3.19 ). remark: if the motor has built-in gear, the number of steps needed to complete one full turn at the output shaft depends on the gear ratio used. table 22. setmode - output state on stop co ntrol register (address 12h) bit description legend: * default value. address register bit access value description 12h setmode 7:2 r/w - reserved 1 r/w 1 outputs = hold after ccw stop 0* outputs = logic 0 after ccw stop 0 r/w 1 outputs = hold after cw stop 0* outputs = logic 0 after cw stop table 23. phcntl - phase control regi ster (address 13h) bit description legend: * default value. address register bit access value description 13h phcntl 7:2 - 0* reserved 1:0 r/w 11 or 10 half-step drive outputs 01 two-phase drive outputs 00* one-phase drive outputs table 24. srotnl, srotnh - steps per rotation control registers (address 14h, 15h) bit description legend: * default value. address register bit access value description 14h srotnl 7:0 r/w 00h* number of steps per one rotation, low byte 15h srotnh 7:0 r/w 00h* number of steps per one rotation, high byte
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 20 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.10 cwpwl, cwpwh ? clockwise step pulse width register this register determines the step pulse width used for the phase sequence output waveforms during clockwise (cw) rotation. this register sets the pulse width value between 3 ? s and 3145 ms ( ? 5%). the upper three bits of the register are the prescaler that determines the dynamic range for the step pulse width. table 26 shows the range for each setting of the prescaler. remark: the values given in table 26 are based on nominal 1 mhz internal clock. this method gives the user access to the entire range with the smallest pulse width (fastest speed) of 3 ? s at the lower end, and the largest pulse width (slowest speed) of 3145 ms at the higher end. the prescaler value defines the range of the ramp control. the ramp-up starts from its maximum pulse width and ramp-down ends at same maximum pulse width. the top speed of the ramp control is defined by both prescaler and step_pulse_width values. final (top) speed = (minimum pulse width in the range defined by prescaler[15:13]) ? (step_pulse_width[12:0] + 1). table 25. cwpwl, cwpwh - clockwise st ep pulse width control register (address 16h, 17h) bit description legend: * default value. address register bit access value description 16h cwpwl 7:0 r/w 00h* step pulse width, low byte 17h cwpwh 7:0 r/w 00h* step pulse width, high byte fig 8. step pulse width table 26. prescaler range settings prescaler [p2:p0] decimal value (d) 2 d range 000 0 1 3 ? s to 24.576 ms 001 1 2 6 ? s to 49.152 ms 010 2 4 12 ? s to 98.304 ms 011 3 8 24 ? s to 196.608 ms 100 4 16 48 ? s to 393.216 ms 101 5 32 96 ? s to 786.432 ms 110 6 64 192 ? s to 1572.864 ms 111 7 128 384 ? s to 3145.728 ms 002aae839 p2 p1 p0 prescaler 13 bits (2 13 = 8192 steps) step pulse width 12 0 15 14 13
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 21 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.11 ccwpwl, ccwpwh ? counter-clockwise step pulse width register this register determines the step pulse width used for the phase sequence output waveforms during counter-clockwise (ccw) rotation. the 16-bit value sets the pulse width between 3 ? s and 3145 ms ( ? 5%). the upper three bits of the register are the prescaler that determines the dynamic range for the step pulse width. table 28 shows the range for each setting of the prescaler. remark: the values given in table 28 are based on nominal 1 mhz internal clock. this method gives the user access to the entire range with the smallest pulse width (fastest speed) of 3 ? s at the lower end, and the largest pulse width (slowest speed) of 3145 ms at the higher end. the prescaler value defines the range of the ramp control. the ramp-up is started from its maximum pulse width and ramp-down ends at same maximum pulse width. the top speed of the ramp control is defined by both prescaler and step_pulse_width values. final (top) speed = (minimum pulse width in the range defined by prescaler[15:13]) ? (step_pulse_width[12:0] + 1). table 27. ccwpwl, ccwpwh - co unter-clockwise step pul se width control register (address 18h, 19h) bit description legend: * default value. address register bit access value description 18h ccwpwl 7:0 r/w 00h* step pulse width, low byte 19h ccwpwh 7:0 r/w 00h* step pulse width, high byte fig 9. step pulse width table 28. prescaler range settings prescaler [p2:p0] decimal value (d) 2 d range 000 0 1 3 ? s to 24.576 ms 001 1 2 6 ? s to 49.152 ms 010 2 4 12 ? s to 98.304 ms 011 3 8 24 ? s to 196.608 ms 100 4 16 48 ? s to 393.216 ms 101 5 32 96 ? s to 786.432 ms 110 6 64 192 ? s to 1572.864 ms 111 7 128 384 ? s to 3145.728 ms 002aae839 p2 p1 p0 prescaler 13 bits (2 13 = 8192 steps) step pulse width 12 0 15 14 13
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 22 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.12 cwscountl, cwscounth ? number of clockwise steps register this register determines the number of steps the motor should turn in clockwise direction. 7.3.13 ccwscountl, ccwscounth ? number of counter-clockwise steps register this register determines the number of steps the motor should turn in counter-clockwise direction. 7.3.14 cwrcountl, cwrcounth ? number of clockwise rotations register this register determines the number of full rotations the motor shou ld turn in clockwise direction. 7.3.15 ccwrcountl, ccwrcounth ? number of counter-clockwise rotations register this register determines the number of full rotations the moto r should turn in counter-clockw ise direction. table 29. cwscountl, cwsco unth - number of clockwise steps count register (address 1ah, 1bh) bit description legend: * default value. address register bit access value description 1ah cwscountl 7:0 r/w 00h* number of clockwise steps, low byte 1bh cwscounth 7:0 r/w 00h* number of clockwise steps, high byte table 30. ccwscountl, ccwscounth - number of counter-clockwise steps count register (address 1ch, 1dh) bit description legend: * default value. address register bit access value description 1ch ccwscountl 7:0 r/w 00h* number of counter-clockwise steps, low byte 1dh ccwscounth 7:0 r/w 00h* number of counter-clockwise steps, high byte table 31. cwrcountl, cwrcounth - number of clockwise rotations count register (address 1eh, 1fh) bit description legend: * default value. address register bit access value description 1eh cwrcountl 7:0 r/w 00h* number of clockwise rotations, low byte 1fh cwrcounth 7:0 r/w 00h* number of clockwise rotations, high byte table 32. ccwrcountl, ccw rcounth - number of counter-clockwise rotations count register (address 20h, 21h) bit description legend: * default value. address register bit access value description 20h ccwrcountl 7:0 r/w 00h* number of counter-clockwise rotations, low byte 21h ccwrcounth 7:0 r/w 00h* number of counter-clockwise rotations, high byte
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 23 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.16 extrasteps0, extrasteps1 ? ex tra steps count for intp0, intp1 control register this register has no effect if the interrupt based motor control is disabled or if the extrasteps feature for that interrupt is disabled. when extrasteps feature is se lected using int_es_setup re gister bits [1:0], the 8-bit value in this register is used to determine the number of steps or rotations to be overdriven. direction of rotation of motor is ma intained. if the count value in this register = 0, no extrasteps occurs. whet her the count indi cates the number of extra steps or number of full rotations depends on the value of int_act_setup control register bit 4. if int_act_setup[4] = 0 (default value), t hen extrastepsn value indicates number of extra steps that will occur after the corresponding interrupt. if int_act_setup[4] = 1, then extrastepsn va lue indicates number of full rotations that will occur after the corresponding interrupt. 7.3.17 rmpcntl ? ramp control register the multiplication factor has a decimal range from 1 to 8192 as shown in ta b l e 3 5 . table 33. extrasteps0, extrasteps1 - extra st eps count for intp0, intp1 register (address 22h, 23h) bit description legend: * default value. address register bit access value description 22h extrasteps0 7:0 r/w 00h* count value for extrasteps (steps or rotations) for intp0 23h extrasteps1 7:0 r/w 00h* count value for extrasteps (steps or rotations) for intp1 table 34. rmpcntl - ramp control register (address 24h) bit description legend: * default value. address register bit access value description 24h rmpcntl 7:6 r only 00* reserved 5 r/w 1 enable ramp-up during start 0* disable ramp-up during start 4 r/w 1 enable ramp-down to stop 0* disable ramp-down to stop 3:0 r/w 0000* ramp step multiplication factor
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 24 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller rmpcntl[5:4] enables/disables the speed ra mp-up during starting of the motor and speed ramp-down during stopping of the motor. the rmpcntl[3:0] defines the acceleration/dec elerating rate of the ramp control. if the value is small, the pwm width decrement (a ccelerating)/increment (decelerating) is slower. the pulse width decrement and increment step is ?smallest_pulse_step ? rmpcntl[3:0]?. the smallest_pulse_step is defined by pr escaler value of cwpw h and ccwpwh. each prescaler setting?s smallest_pulse_step is given in ta b l e 2 6 and ta b l e 2 8 (the minimum value of the range). the ramp control will start and end in spe ed of maximum_pulse_ step, which is the maximum value of the range given in table 26 and ta b l e 2 8 . the ramp-up is completed when the pulse width gets the width that is set by cwpwl/cwpwh or ccwpwl/ccwpwh registers. during ramp-up, the step pulse width is automatically decremen ted (from the maximum value for step pulse width in the chosen ra nge) until the value in cwpw or the ccwpw register is reached, depending on the direction of rotation. see figure 10 . during ramp-down, the step pulse width is automatically incremented from the current value in cwpw or the ccwpw, depending on the direction of rotation, until it reaches the maximum value for step pulse width in the chosen range. see figure 10 . table 35. multiplication factor value for ramp-up, ra mp-down control register value [3:0] decimal value (d) ramp step multiplication factor (2 d ) 0000 0 1 0001 1 2 0010 2 4 0011 3 8 0100 4 16 0101 5 32 0110 6 64 0111 7 128 1000 8 256 1001 9 512 1010 10 1024 1011 11 2048 1100 12 4096 1101 13 8192 1110, 1111 14, 15 reserved and do not use
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 25 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller example shown is one-phase drive for clockwise rotation. (1) the ramp start or ramp end speed is defined as the maximum value of the range given in table 26 and table 28 based on prescaler bits [15:13] in cwpwh/ccwpwh registers. for example, the ramp start or ramp end speed is 98.304 ms if the cwpwh/ccwpwh[15:13] = 010. (2) the decrease/increase step pulse width is defin ed as the minimum value of the range given in table 26 and table 28 based on prescaler bit s [15:13] in cwpwh/ccwpwh registers times the ramp step multiplication factor bits [3:0] in rmpcntl register. for example, the decrease/incre ase step pulse width is 192 ? s(12 ? s ? 16) if the cwpwh/ccwpwh[15:13] = 010 (minimum value 12 ? s) and rmpcntl[3:0] = 0100 (multiplication factor 16). (3) the ramp-up final speed is defined as t he minimum value of the range given in table 26 and ta b l e 2 8 based on prescaler bit s [15:13] times the step pulse width value bits [12:0] plus 1 in cwpwh/l and ccwpwh/l regist ers. for example, the ramp-up final speed is 24 ? s (12 ? s ? 2) if the cwpwh/ccwpwh[15:13] = 010 (minimum value 12 ? s) and the cwpwh/l or ccwpwh/l = 0x0001 (1 + 1). fig 10. pca9629 operation model for ramp-up (acceleration) and ramp-down (deceleration) 002aaf871 speed time duration to keep rotation/step in final speed defined by cwscountx/ccwscountx and cwrcountx/ccwrcountx registers ramp-up final (top) speed (3) ramp-down (no microcontroller interactions required) ramp start speed (1) ramp end speed (1) start motor if mcntl[7] = 1 stop motor when operation is completed and mcntl[7] bit is self-clear increase step pulse width (2) (deceleration rate) decrease step pulse width (2) (acceleration rate) 98.304 ms 97.536 ms 98.112 ms 97.92 ms 97.728 ms out0 out1 out2 out3 ramp-up operation 98.304 ms 97.536 ms 98.112 ms 97.92 ms 97.728 ms final speed ramp-down operation 24 s 24 s
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 26 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller during ramp-up and ramp-down phase of operat ion, the interrupt based controls do not affect the motor run. an interrupt can happen during ramp-up or ramp-down and it gets registered in the chip. once the ramp-up opera tion is finished, then the interrupt is acted upon. a stop request from the microcontroller (writing mcntl[7] to ?0?) is the only event that affects the motor operation during ramp-up and ramp-down. during ramp-up, the micro can issue a stop request. the following sequence of events takes place in the given order: 1. if hard stop is enabled, the motor stops immediately (even if ramp-down is enabled) - priority 1. 2. if hard stop is disabled but ramp-down is enabled, then the motor starts to ramp down to a stop - priority 2. 3. if hard stop is disabled and ramp-down is disabled, then motor stops immediately - priority 3. during ramp-down, the micro can issue a st op request. the following sequence of events takes place in the given order: 1. if hard stop is enabled, the motor stops i mmediately (it does not finish ramping down) - priority 1. 2. if hard stop is disabled but ramp-down is enabled, then the motor continues to ramp down to a stop - priority 2. in the duration between end of ramp-up and be ginning of ramp-down, the interrupt based controls (if enabled) can affect the operation of the motor. in this region, section 7.3.6 gives the priority of events when both in terrupt based control and ramp control are enabled together. 7.3.18 loopdly ? loop delay timer register this feature is used to make the motor wait for a certain amou nt of time before reversing its direction of rotation. there are two situ ations in which the motor must reverse its direction of rotation: ? the user requests both clockwise and count er clockwise rotation (also known as auto reversal mode). ? on an interrupt (also known as interrupt reversal mode). this register holds the wait time value in seconds. 00h = 0 second wait time. ffh = 255 seconds wait time. remark: loopdly has an accuracy of ? 5%. table 36. loopdly - loop delay timer contro l register (address 25h) bit description legend: * default value. address register bit access value description 25h loopdly 7:0 r/w 00h* loop delay counter
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 27 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.19 mcntl ? motor control register this register acts like the master control panel for driving the motor. it determines the type of motor operation and controls the starting /stopping of the motor. the registers from address 0eh (int_act_setup) to 25h (loopdly) are referred to as the motor parameter registers. the user must first pr ogram the motor parameter registers that are required for the current run of the motor. after th at, this register should be programmed with the type of operation required. the motor starts when bit 7 of this register is set. 7.3.19.1 mcntl[7]: start/stop motor this bit indicates the state of the motor. a ?1? indicates that the motor is running and ?0? indicates that the motor is in the stopped state. to start the motor, write ?1? to this bit. once the motor is started, any changes to the motor parameter registers do not affect the current run of the motor except for phase changes. only phase changes (using the phcntl regi ster) are allowed durin g motor operation. similarly, bits [6:0] of the mcntl register cannot be chan ged during motor operation. the only bit that can be changed in the mcntl re gister while the motor is running is this start/stop bit. also, any restart command (writing ?1? to this bit when it is already set), before the completion of the current operation are ignored. when the current operation is completed, th e motor stops and this bit is cleared. the completion of motor operation can be checked by reading this bit. after the motor has stopped, the motor parameter registers can be updated and the motor can be started again. the microcontroller can stop the motor at any time by writing ?0? to this bit (this is referred to as a stop request). once the motor stops, this bit is cleared. stop request issued when the motor is already in the stopped state is ignored. table 37. mcntl - motor control regist er (address 26h) bit description legend: * default value. address register bit access value description 26h mcntl 7 r/w 1 start motor 0* stop motor 6 r only 0* reserved 5 r/w 1 hard stop enabled 0* hard stop disabled 4 r/w 1 perform the actions specified in bits [3:0] continuously 0* perform the actions specified in bits [3:0] once 3:2 r/w 11 or 10 step pulses and then rotations 01 rotate for specified number of rotations 00* send specified number of step pulses 1:0 r/w 11 rotate counter-clockwise first, then clockwise 10 rotate clockwise first, then counter-clockwise 01 rotate counter-clockwise 00* rotate clockwise
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 28 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.3.19.2 mcntl[5]: hard stop the ?hard stop? feature is only applicable for st op requests issued by the micro. it does not affect the interrupt based stop mechanism. th is feature is used to stop the motor immediately when the micro issues a stop requ est. hard stop feature has a higher priority over ramp down. so even if ramp down is enabled, if the micro issues a stop request, the motor stops immediately and does not ramp do wn to stop. the micro should decide how the part should handle its stop request and accordingly enable/disable this feature. the priority of events during a stop request is: ? if hard stop is enabled (mcntl[5]) , then the motor stops immediately. ? if ramp down is enabled (r mpcntl[4]), the motor starts ramping down to a stop. 7.3.19.3 mcntl[4]: continuous operation this bit determines if the operation specified in bits [3:0] of this register is executed once or continuously. if continuous operation is enabled, the motor can be stopped either by issuing a stop request or if an interrupt happens and the motor is programmed to stop on that interrupt. if continuous ope ration is not enabled then, the motor stops automatically after finishing the current operation once. 7.3.19.4 mcntl[3:2]: steps and/or rotations these two bits determine how many steps and/or rotations are executed by the motor in the current run. based on clockwise or coun ter-clockwise direction (mcntl[1:0]), the clockwise registers (cwscount, cwrco unt) or counter-clockwise registers (ccwscount, ccwrcount) are used to determine the number steps/rotations. the following rules should be observed while programming these bits: ? requested operation is steps (mcntl[3:2] = 00): number of steps should be non zero in the direction of operation (cw or ccw). in auto/interrupt based reversal modes (cw and ccw), the number of steps in both directions should be non zero. if this condition is not satisf ied, the motor does not start. ? requested operation is rotations (mcntl[3:2 ] = 01): number of rotations should be non zero in the direction of operation (cw or ccw). in auto/interrupt based reversal modes (cw and ccw), the number of rotations in both directions should be non zero. if this condition is not satisfied, the motor does not start. ? requested operation is steps and rotations (mcntl[3:2] = 10 or 11): at least one of the parameters, steps or rotations, should be a non zero value in the direction of operation. in auto/interrupt based reversal modes (cw and ccw), the same rule applies to both directions. if this condition is not satisfied, the motor does not start. 7.3.19.5 mcntl[1:0]: clockwise (c w) / counter-clockwise (ccw) these two bits are used to program the direction of the motor for current operation. options 10 and 11 are called auto reversal modes (to differentiate it from interrupt based reversal). in these modes, the motor starts rotating in one direction and after completing the required steps/rotations reverses the direction of rotation. if continuous mode of operation is programmed with auto reversal, then the motor keeps repeating the operation continuously.
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 29 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.4 motor coil excitation initially, after a power-up of the device, when the motor is started for the first time, the first coil that is energized is out0 (if the motor is turning in the clockwis e direction), or out3 (if the motor is turning in th e counter clockwise direction). this very first step (after a power-up) is not counted towards the number steps the motor is required to move (it is the reference step). all subsequent steps are all co unted. this applies only for the very first time the motor is st arted after the device is powered up. for all subsequent starting of the motor, the first coil that is energized is the same coil where it had stopped. for example, consider the motor running in cl ockwise direction in the one-phase drive mode. if the last coil that was energized before the motor stopped was out2, then when the motor is started again out2 is energized first and after the pulse width time elapses the next coil in sequence, that is, out3 is energized. 7.5 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9629 in a reset condition until v dd has reached v por . at that point, the rese t condition is released and the pca9629 registers and state machin e initialize to their default states. the power-on reset typically completes the reset and enables the part by the time the power supply is above v por . however, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 2 v typical. remark: the system level reset pulse should be > 4 ? s for the chip to guarantee reset condition. 7.6 reset input a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the pca9629 registers and i 2 c-bus state machine are held in their default state until the reset input is once again high. the reset input has a 200 k ? internal pull-up to v dd pin. the maximum wait time after reset pin is released is 1 ms (typical).
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 30 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.7 software reset the software reset call allows all the devices in the i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. to be pe rformed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the maximum wait time after so ftware reset is 1 ms (typical). the swrst call function is defined as the following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved general call i 2 c-bus address ?0000 000? with the r/w bit set to ?0? (write) is sent by the i 2 c-bus master. 3. the pca9629 device(s) acknowledge(s) after seeing the general call address ?0000 0000? (00h) only. if the r/w bit is set to ?1? (read), no acknowledge is returned to the i 2 c-bus master. 4. once the general call address has been sent and acknowledged, the master sends one byte. the value of the byte must be equal to 06h. the pca9629 acknowledges this value only. if the byte is not equal to 06h, the pca9629 does not acknowledge it. if more than one byte of data is sent, the pca9629 does not acknowledge anymore. 5. once the right byte has been sent and correctly acknowledged, the master sends a stop command to end the software reset sequence: the pca9629 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. if the master sends a repeated start instead, no reset is performed. the i 2 c-bus master must interpret a non-acknowledge from the pca9629 (at any time) as a ?software reset abort?. the pca9629 does not initiate a software reset. 7.8 interrupt output the open-drain active low interrupt is activated by the following two mechanisms: ? watchdog timer: if the watchdog timer is enabled and the timer times out, then an interrupt is generated and the watchdog interrupt flag bit [3] is set in the watchdog control register (wdcntl). ? gpios: one or more of pins p0 to p3 can generate an interrupt if the following conditions are met: ? the pin is configured as an input in the i/o configuration register (ioc). ? the interrupt from that pin is enabled in the mask interrupt register (msk). ? the pin?s state change (rising edge or falling edge) is programmed to generate an interrupt in the interrupt mode register (intmode). the interrupt int pin output can be enabled or disa bled using mode register bit [5] (0 = enable; 1 = disable). the interrupt flag bit is set in the intstat register when one of the interrupts is generated from p0 to p3. remark: if the state of the pin does not match th e contents of the input port register, changing an i/o from an output to an input may cause a false interrupt to occur.
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 31 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.9 phase sequence generator the pca9629 phase seque nce generator uses th e on-chip oscillator and control logic to generate logic waveforms needed to support the following three types of stepper motor drive formats: ? one-phase drive, also called ?wave drive? ? two-phase drive ? half-step drive these logic level outputs are used to drive high current power driver stages to provide required drive current to the stepper motor coils. 7.9.1 one-phase drive (wave drive) in one-phase drive method, only one windi ng is energized at any given time. the advantage of wave drive mode is its simplicity. the disadvan tage of wave drive mode is that in the unipolar wound motor only 25 %, and in the bipolar motor only 50 % of the total motor winding are used at any given time. th is means that maximu m torque output from the motor is not made available. since only one winding is energized, holding torque and working torque are reduced by 30 %. this can, within limits, be compensated by increasing supply voltage. the advantage of this form of drive is higher efficiency, but at the cost of reduc ed step accuracy. number of steps shown = 4 for simplicity. fig 11. wave drive step sequence waveforms table 38. logic output sequence for wave drive winding step 1 2 3 4 5 6 7 8 winding d 10001000 winding c 01000100 winding b 00100010 winding a 00010001 a b c d step pulses output a output b output c output d output disabled rotor position 002aae757
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 32 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 7.9.2 two-phase drive in two-phase drive method, two windings are energized at any given time. in case of two-phase drive, the torque output of the un ipolar wound motor is lower than the bipolar motor (for motors with the same winding parameters) since the unipolar motor uses only 50 % of the available winding, while the bipolar motor uses the entire winding. 7.9.3 half-step drive (one-phase and two-phase on) ?half-step drive? combines both wave and two-phase (one-phase and two-phase on) drive modes. this results in angular movements that are half of those in 1- or 2-phases-on drive modes. half-stepping can reduce a phenomen on referred to as resonance, which can be experienced in 1- or 2-phases-on drive modes. as the name implies, in this m ode it is possible to step a motor in a half-step sequence, thus producing half steps, for example 3.75 ? steps from a 7.5 ? motor. a possible drawback for some applications is that the holding torque is alternately strong and weak on successive motor steps. this is because on full steps only one phase winding is energized, while on the half-steps two stator windings are energized. also, because current and flux paths differ on alternate steps, accuracy is worse than when full stepping. number of steps shown = 4 for simplicity. fig 12. two-phase drive step sequence waveforms table 39. logic output sequence for two-phase drive winding step 1 2 3 4 5 6 7 8 winding d 10011001 winding c 11001100 winding b 01100110 winding a 00110011 a b c d step pulses output a output b output c output d output disabled rotor position 002aae758
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 33 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller four step stepper motor run with half-step waveforms increases the number of steps to eight. fig 13. half-step drive sequence waveforms table 40. logic output sequence for half-step drive winding step 1 2 3 4 5 6 7 8 winding d 11000001 winding c 01110000 winding b 00011100 winding a 00000111 d c b a step pulses output d output c output b output a output disabled rotor position 002aae759
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 34 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 8. characteristics of the i 2 c-bus the i 2 c-bus is for two-way, two- line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 14 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 15 ). 8.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 16 ). fig 14. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 15. definition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 35 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 8.3 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. ea ch byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. 9. bus transactions data is transmitted to the pca9629 registers using ?write byte? transfers. data is read from the pca9629 regi sters using ?read byte? transfers. fig 16. system configuration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 17. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 36 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 10. application design-in information 10.1 stepper motor coil driver considerations when choosing a motor and coil driver circuit fo r an application, it is necessary to choose the coil driver such that the minimum expected drive strength of the coil driver over the anticipated operating conditions exceeds the minimum coil current in the application. for the nmos fets, the gate voltage affects the fet drive strength, so it is necessary to evaluate the fet with its gate at the minimum v dd planned for the pca9629 application, because the pca9629 cannot drive the gate higher than the v dd . for example, in most applicat ions a 5 v power supply would have a specification like 5v ? 10 % or 5 v ? 20 %, so it would be necessary to verify that the on-resistance or current sinking capability of the fet with a gate voltage of 4.75 v or 4.5 v, whichever applies, is capable of sinking all of the curr ent that the motor might require. since fets present a capacitive load to the outputs of the pca9629, the output asymptotically approaches the v dd of the part, so eventually the full v dd appears at the output. however, for darlington bipolar coil drivers the input current represents a static current load that reduces the v oh . so depending upon the input current of the darlington bipolar coil driver, the pca9629 output voltage will always be less than v dd . this in turn reduces the input current and also reduces the available drive current from the darlington bipolar coil driver, so the lowest gain for the driver and the input current gain product must be considered in verifying that the maximum motor current can be sunk by the driver. device address configured as 0100 0000b for this example. fig 18. typical application 002aae760 pca9629 v dd scl sda int reset ad1 ad0 master controller v ss p0 p1 p2 p3 12 v external high current driver generates intp1 sensor 1 electrical stepper motor position b sensor 0 generates intp0 position a out0 out1 out2 out3 5 v 2 k 1.1 k 1.6 k 1.6 k 3.3 v int rst m
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 37 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 10.2 considerations when using gpio pins p0 to p3 as inputs for proper operation of gpio pins as inputs, the signals at the inputs must be free from any glitches or noise. the signals must be logic level inputs. for example, outputs from sensors must provid e logic level signals at the input pins of pca9629. this may require signal condition ing at the outputs of sensors. another example is when using p0 to p3 for key switch sensing. the inputs of pca9629 do not provide key de-bouncing. this is external to pca9629 and is user-defined and supplied. 10.3 priority of ramp control, interr upt-based control, loop delay and hard stop during ramp-up and ramp-down phases of operation, the interrupt-based controls do not affect the motor run. interrup ts that occur during ramp-up or ramp-down are ignored. once the ramp-up operation is finished (when the moto r is running at the final speed), then the interrupts that occur are acted upon. a stop re quest from the microcontroller (writing 0 to mcntl[7]) is the only event that affects the motor operation during ramp-up and ramp-down. during ramp-up, the microcontroller can issue a stop request. the following sequence of events takes place in the given order: 1. if hard stop is enabled, the motor stops im mediately (even if ramp-down is enabled); priority 1. 2. if hard stop is disabled but ramp-down is enabled, then the motor starts to ramp down to a stop; priority 2. 3. if hard stop is disabled and ramp-down is disabled, then motor stops immediately; priority 3. during ramp-down, the microcontroller can issue a stop request. the following sequence of events takes place in the given order: 1. if hard stop is enabled, the motor stops imme diately (it does not finish ramping down); priority 1. 2. if hard stop is disabled but ramp-down is enabled, then the motor continues to ramp down to a stop; priority 2. in the duration between end of ramp-up and be ginning of ramp-down, the interrupt-based controls (if enabled) can affect the operation of the motor. in this region, section 7.3.6.2 gives the priority of events when both interrupt-based control and ramp control are enabled together. consider the following exam ple (the motor is programmed to reverse rotation on an interrupt): ? motor programmed for cw rotations; ramp-up and ramp-down enabled; reverse rotation on interrupt p0/p1. ? when motor is started, it starts ramping up and when ramp-up is completed it rotates at the final speed. ? if interrupt p0 happens, then it reverses rotation right away and start rotating in the ccw direction for the specified number of rotations.
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 38 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller ? before the specified number of rotations is co mpleted in the ccw dire ction, if interrupt p1 happens, then it again reverses its rota tion right away and start rotating in the cw direction for the specified number of rotations. ? if no other interrupt happens, the motor fi nishes executing the specified number of rotations in the cw direction and then starts to ramp down. in the above example, if extra steps are enab led for interrupts p0 and p1, then when the interrupts happen the motor execut es the extra steps in the cu rrent direction of rotation and then reverses its direction. 11. limiting values 12. static characteristics table 41. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.0 v v i/o voltage on an input/output pin v ss ? 0.5 5.5 v i i/o input/output current pn, outn, int , scl, sda - ? 50 ma i i input current - ? 20 ma i ss ground supply current - 210 ma p tot total power dissipation - 400 mw t stg storage temperature ? 65 +150 ?c t amb ambient temperature ? 40 +85 ?c table 42. static characteristics v dd = 4.5 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; no load; f scl = 1 mhz; v dd =5.5v -610ma i stb standby current no load; f scl = 0 khz; v i =v dd or v ss ; v dd =5.5v -12ma v por power-on reset voltage no load; v i =v dd or v ss -2.3-v v pdr power-down reset voltage no load; v i =v dd or v ss [1] -2.0-v input scl; input/output sda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v ol = 0.4 v; v dd =5.0v 30 40 - ma i l leakage current v i =v dd or v ss ? 1-+1 ? a c i input capacitance v i =v ss -610pf
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 39 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller [1] in order to reset part, v dd must be lowered to 1.4 v. [2] each bit must be limited to a maximum of 25 ma and the to tal package limited to 210 ma due to internal busing limits. [3] for i oh = ? 25 ma, the minimum v oh = v dd ? 0.7 v with v dd = 4.5 v to 5.5 v. out0 to out3 outputs i ol low-level output current v ol = 0.5 v; v dd =4.5v [2] 25 28 - ma i ol(tot) total low-level output current v ol = 0.5 v; v dd =4.5v [2] - - 120 ma v oh high-level output voltage i oh = ? 10 ma; v dd =4.5v [3] 4.0 - - v p0 to p3 i/os i ol low-level output current v ol = 0.5 v; v dd =4.5v [2] 25 28 - ma i ol(tot) total low-level output current v ol = 0.5 v; v dd =4.5v [2] - - 120 ma v oh high-level output voltage i oh = ? 10 ma; v dd =4.5v [3] 4.0 - - v i oz off-state output current 3-state; v oh =v dd or v ss ? 10 - +10 ? a c io input/output capacitance 3-state pins as inputs - 5 8 pf address inputs v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1-+1 ? a c i input capacitance - 3 5 pf reset input v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1-+1 ? a c i input capacitance - 3 5 pf i lil low-level input leakage current v i =v ss ? 7- ? 45 ? a int output i ol low-level output current v ol = 0.5 v; v dd =4.5v 24 28 - ma i oh high-level output current open-drain; v oh =v dd ? 10 - +10 ? a c o output capacitance - 5 - pf table 42. static characteristics ?continued v dd = 4.5 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit fig 19. out[0:3] output equival ent circuit fig 20. p[0:3] input/output equivalent circuit 002aag587 data[0:3] output control out[0:3] (output) v dd = 5.0 v pmos nmos 002aag588 data[0:3] i/o control p[0:3] (i/o) v dd = 5.0 v pmos nmos enable input data [0:3]
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 40 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 13. dynamic characteristics [1] minimum scl clock frequency is limited by t he bus time-out feature, which resets the serial bus interface if either sda or s cl is held low for a minimum of 25 ms. disable bu s time-out feature for dc operation. [2] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [3] t vd;dat = minimum time for sda data out to be valid following scl low. [4] in order to bridge the undefined region of the scl falling edge, a master device must internally provide a hold time of at l east 300 ns for the sda signal (refer to the v il of the scl signal). [5] the maximum t f for the sda and scl bus lines is specif ied at 300 ns. the maximum fall time (t f ) for the sda output stage is specified at 250 ns. this allows series protection resi stors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum specified t f . [6] c b = total capacitance of one bus line in pf. [7] input filters on the sda and scl inputs suppress noise spikes less than 50 ns. [8] the time delay from one of the p[1:0] inputs edge changes to the motor control outputs out[3:0] change. typical value = 6.5 ? s. table 43. dynamic characteristics v dd = 4.5 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. oscillator frequency = 1 mhz ? 5 % at 25 ? c (see figure 23 ). symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency [1] 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - ? s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - ? s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - ? s t hd;dat data hold time 0 - 0 - 0 - ns t vd;ack data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 ? s t vd;dat data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 ? s t su;dat data set-up time 250 - 100 - 50 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - ? s t high high period of the scl clock 4.0 - 0.6 - 0.26 - ? s t f fall time of both sda and scl signals [4] [5] - 300 20 + 0.1c b [6] 300 - 120 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [6] 300 - 120 ns t sp pulse width of spikes that must be suppressed by the input filter [7] -50 -50-50ns t d(o) output delay time interrupt based motor control latency [8] 5.7 7.4 5.7 7.4 5.7 7.4 ? s reset t w(rst) reset pulse width [9] 14 1414 ? s t rec(rst) reset recovery time - 1 - 1 - 1 ms
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 41 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller [9] the internal glitch filter rejects any low pulse less than 1 ? s. the system level reset pulse should be > 4 ? s for the chip to guarantee reset condition. fig 21. definition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd fig 22. reset timing sda scl 002aag778 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset p0 to p3 output off start ack or read cycle fig 23. typical oscillator frequency versus temperature 1.000 0.975 1.025 1.050 f osc (mhz) 0.950 t amb (c) -40 85 60 10 35 -15 002aag081 25
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 42 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 14. test information r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 24. test circuitry for switch ing times for gpio pins p0 to p3 r l for sda and scl = 165 ? (30 ma or less current). c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 25. test circuitry for swit ching times for sda and scl pulse generator v o c l 50 pf r l 500 002aac019 r t v i v dd dut 2v dd open v ss 500
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 43 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 15. package outline fig 26. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 44 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 45 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 27 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 4 and 45 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 27 . table 44. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 45. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 46 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 18. abbreviations msl: moisture sensitivity level fig 27. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 46. abbreviations acronym description ai auto-increment ccw counter-clockwise cdm charged-device model cmos complementary metal-oxide semiconductor cpu central processing unit cw clockwise dmos double-diffused metal-oxide semiconductor dut device under test esd electrostatic discharge fet field-effect transistor fm+ fast-mode plus gpio general purpose input/output hbm human body model hvac heating, venting and air conditioning i/o input/output i 2 c-bus inter-integrated circuit bus ic integrated circuit led light emitting diode lsb least significant bit
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 47 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 19. revision history nmos negative-channel metal-oxide semiconductor msb most significant bit pcb printed-circuit board pps pulses per second pwm pulse width modulator por power-on reset table 46. abbreviations ?continued acronym description table 47. revision history document id release date data sheet status change notice supersedes pca9629 v.1 20120229 product data sheet - -
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 48 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 49 of 51 nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pca9629 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 29 february 2012 50 of 51 continued >> nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 command register . . . . . . . . . . . . . . . . . . . . . . 6 7.3 register definitions . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 mode ? mode register . . . . . . . . . . . . . . . . . . 8 7.3.1.1 disable interrupt output pin (bit 5) . . . . . . . . . . 8 7.3.1.2 outputs change on stop (bit 4) . . . . . . . . . . . 8 7.3.2 subadr1 to subadr3 ? i 2 c-bus subaddress 1 to 3 . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.3 allcalladr ? all call i 2 c-bus address . . . . 9 7.3.4 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.4.1 wdtoi ? watchdog time-out interval register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.4.2 wdcntl ? watc hdog control register . . . . 11 7.3.5 gpios and interrupts . . . . . . . . . . . . . . . . . . . 12 7.3.5.1 ip ? input port register . . . . . . . . . . . . . . . . . 12 7.3.5.2 intstat ? interrupt stat us register . . . . . . . 12 7.3.5.3 op ? output port register . . . . . . . . . . . . . . . 12 7.3.5.4 ioc ? i/o conf iguration register . . . . . . . . . . 13 7.3.5.5 msk ? mask interrupt register. . . . . . . . . . . . 13 7.3.5.6 clrint ? clear interrupts register . . . . . . . . 14 7.3.5.7 intmode ? interrupt mode register . . . . . . . 14 7.3.6 interrupt based motor control . . . . . . . . . . . . . 15 7.3.6.1 int_act_setup ? interrupt action setup control register . . . . . . . . . . . . . . . . . . . 16 7.3.6.2 int_mtr_setu p ? interrupt motor setup control register . . . . . . . . . . . . . . . . . . . 16 7.3.6.3 int_es_setup ? interrupt extra steps setup control register . . . . . . . . . . . . . . . . . . . 17 7.3.6.4 int_auto_clr ? interrupt auto clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3.7 setmode ? output state on stop control register . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.8 phcntl ? phase control register . . . . . . . . 19 7.3.9 srotnl, srotnh ? steps per rotation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.10 cwpwl, cwpwh ? clockwise step pulse width register. . . . . . . . . . . . . . . . . . . . . 20 7.3.11 ccwpwl, ccwpwh ? counter-clockwise step pulse width register . . . . . . . . . . . . . . . . 21 7.3.12 cwscountl, cwscounth ? number of clockwise steps register . . . . . . . . . . . . . . . 22 7.3.13 ccwscountl, ccwscounth ? number of counter-clockwise steps register . . . . . . . . 22 7.3.14 cwrcountl, cwrcounth ? number of clockwise rotation s register . . . . . . . . . . . . 22 7.3.15 ccwrcountl, ccwrcounth ? number of counter-clockwise rotations register. . . . . . 22 7.3.16 extrasteps0, extrasteps1 ? extra steps count for intp0, intp1 control register 23 7.3.17 rmpcntl ? ramp control register . . . . . . . 23 7.3.18 loopdly ? loop delay timer register . . . . . 26 7.3.19 mcntl ? motor control register . . . . . . . . . . 27 7.3.19.1 mcntl[7]: start/stop motor . . . . . . . . . . . . . . 27 7.3.19.2 mcntl[5]: hard stop . . . . . . . . . . . . . . . . . . . 28 7.3.19.3 mcntl[4]: continuous operation . . . . . . . . . . 28 7.3.19.4 mcntl[3:2]: steps and/or rotations . . . . . . . . 28 7.3.19.5 mcntl[1:0]: clockwise (cw) / counter-clockwise (ccw) . . . . . . . . . . . . . . . 28 7.4 motor coil excitation . . . . . . . . . . . . . . . . . . . . 29 7.5 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 29 7.6 reset input . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.7 software reset . . . . . . . . . . . . . . . . . . . . . . . . 30 7.8 interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 30 7.9 phase sequence generator . . . . . . . . . . . . . . 31 7.9.1 one-phase drive (wave drive) . . . . . . . . . . . . 31 7.9.2 two-phase drive. . . . . . . . . . . . . . . . . . . . . . . 32 7.9.3 half-step drive (one-phase and two-phase on) . . . . . . . . . . . 32 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 34 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1.1 start and stop conditions. . . . . . . . . . . . . 34 8.2 system configuration . . . . . . . . . . . . . . . . . . . 34 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 35 10 application design-in information . . . . . . . . . 36 10.1 stepper motor coil driver considerations . . . . 36 10.2 considerations when using gpio pins p0 to p3 as inputs . . . . . . . . . . . . . . . . . . . . . 37 10.3 priority of ramp control, interrupt-based control, loop delay and hard stop. . . . . . . . . . 37 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 12 static characteristics . . . . . . . . . . . . . . . . . . . 38 13 dynamic characteristics. . . . . . . . . . . . . . . . . 40 14 test information . . . . . . . . . . . . . . . . . . . . . . . 42
nxp semiconductors pca9629 fm+ i 2 c-bus stepper motor controller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 february 2012 document identifier: pca9629 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 43 16 handling information. . . . . . . . . . . . . . . . . . . . 44 17 soldering of smd packages . . . . . . . . . . . . . . 44 17.1 introduction to soldering . . . . . . . . . . . . . . . . . 44 17.2 wave and reflow soldering . . . . . . . . . . . . . . . 44 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 44 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 45 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 47 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 48 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 48 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 21 contact information. . . . . . . . . . . . . . . . . . . . . 49 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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